1. Field of the Invention
The present invention relates to multiple time programming (MTP) memory cells, and more particularly, to a logic-based MTP memory cell compatible with generic complementary metal-oxide-semiconductor (CMOS) processes.
2. Description of the Prior Art
As diverse types of circuit blocks are integrated into single integrated circuits (ICs), it becomes desirous to integrate non-volatile memory blocks with logic function blocks. However, many non-volatile memory processes require stacked gate structures, which are not available in conventional logic gate fabrication processes, e.g. semiconductor processes using only one polysilicon layer and no special charge-trapping structures.
U.S. Pat. Nos. 7,382,658 (hereinafter '658), 7,391,647 (hereinafter '647), 7,263,001 (hereinafter '001), 7,423,903 (hereinafter '903), 7,209,392 (hereinafter '392) teach various architectures for forming memory cells. '658 teaches one p-type access transistor sharing its floating gate with one n-type metal-oxide-semiconductor capacitor (n-MOSC). '647 teaches one p-type access transistor with one p-type metal-oxide-semiconductor capacitor (p-MOSC) and one n-MOSC. '001 teaches one p-type access transistor sharing a floating gate with two p-MOSCs. '903 teaches a p-type field effect transistor (P-FET) for programming through channel hot electron (CHE) injection, and an n-type field effect transistor (N-FET) for erasing through Fowler-Nordheim (FN) tunneling. '392 teaches one n-type metal-oxide-semiconductor field effect transistor (n-MOSFET) sharing its floating gate with one p-type metal-oxide-semiconductor field effect transistor (p-MOSFET), each transistor coupled to its own access transistor.
Please refer to FIG. 1, which is a diagram of a non-volatile memory cell shown in '392. The non-volatile memory cell comprises a first p-type metal-oxide-semiconductor (PMOS) transistor T1, a second PMOS transistor T2, a first n-type metal-oxide-semiconductor (NMOS) transistor T3, and a second NMOS transistor T4. The first PMOS transistor T1 and the first NMOS transistor T3 are access transistors for the second PMOS transistor T2 and the second NMOS transistor T4, respectively, and are controlled by a control voltage VSG. Input terminals of the first PMOS transistor T1 and the first NMOS transistor T3 receive a select line voltage VSL, and input terminals of the second PMOS transistor T2 and the second NMOS transistor T4 receive a first bit line voltage VBL1 and a second bit line voltage VBL2, respectively. The second NMOS transistor T4 and the second PMOS transistor T2 share a floating gate.